Lynn Reed, President

The Hunt for SCR

This is a story of how we inadvertently created an SCR while using externally sourced physical IP, and how we discovered and fixed it.

Background

SCR stands for Silicon Controlled Rectifier. It consists of a PNPN structure, as contrasted to bipolar transistors with a NPN or PNP structure. Once a SCR has been triggered, it remains on until an external event stops the current. Almost all CMOS circuits have parasitic SCRs everywhere in the layout. A P diffusion in the N-Well, in the P-substrate, next to a N diffusion creates a parasitic SCR. The key is to avoid triggering the SCR. This is done by adding substrate contacts to the wells to prevent voltage drops that might allow a P or N diffusion from becoming forward biased. Particular attention has to be paid to N-Wells that are connected to a supply other than Vdd.

Our Circuit

We designed a specialty 5-volt memory consisting of an 8K byte RAM, and a shadow EEPROM that could write or recall all 64K bits in a single operation. The design contained EEPROM IP, and an analog section that generated timing and monitored the power supply. The EEPROM IP consisted of a bit cell, and a driver cell that switched power supplies from 5 volts to a charge pump to program the EEPROM. In our application, we wanted to drive 256 cells instead of the recommended 16 bits. We ran spice, and the switching waveforms looked satisfactory.

The First Pass SCR Problem

The first silicon came back, and whenever the supply exceeded about 5 volts, and we did a store function, the part latched up, drawing amperes of current. Below 5 volts the part worked as expected. We reviewed the layout and DRCs, but did not find anything wrong.

So, we sent the part to a failure analysis lab, and asked them to identify where the current was flowing. They came back with thermal images showing current flow in the analog portion of the chip. We didn’t see anything wrong in that area, but we massively increased the number of substrate contacts to minimize the possibility of any forward biased N-Wells in the area. We also added a number of test points that allowed us to disable and bypass portions of the analog circuitry in case we still had a problem.

The Second Pass Problem

We made new silicon, which still exhibited SCR characteristics. And our bypass circuits had no effect. We went back to the failure analysis lab with special hardware that allowed us to trigger the SCR. This time, thermal imaging showed a portion of the RAM array in SCR mode. The initial failure analysis had taken images of the chip when it was not in SCR mode, and had identified the small currents that were present in the opamps and bias circuitry in our analog design. This led to the mistaken assumption that the SCR was in the analog area.

We analyzed the area indicated in the thermal imaging, and again, found nothing wrong with the layout. We analyzed the design, and discovered that an illegal condition of storing and recalling at the same time could result in a high current condition. Calculations showed that the currents caused by this condition were in the ampere level, and might be mistaken for an SCR. Could this be the problem that we were attributing to an SCR? We thought so, and redesigned the controller to ensure that a store and a recall could never occur at the same time.

The Third Pass Problem

We made new silicon, and it still had an SCR. So, we returned to the failure analysis lab. We used FIB (Focused Ion Beam technology) to put pads on every node we could think of for microprobing. And every signal looked fine until we did a store command, after which the part latched up.

While we were at the lab, we took multiple thermal images. While doing this, we noticed that the area that had an SCR was related to the current limit we had on the power supply. With very low current limits on the supply (10 mA), we saw the SCR move from the RAM to one of the IP cells we were using to control the EEPROM. Still, even in the IP cell, the layout was correct, and there was no reason for an SCR to be there.

Since we had seen the SCR area move once, we assumed that it could have moved twice, and began studying the IP to determine if there was the possibility of an initial SCR elsewhere. Our theory was that since an SCR causes local distortion of the power busses, we could have an initial SCR, which triggered another, stronger SCR, which in turn shut off the weaker initial SCR. Then, this second SCR triggered a stronger SCR in our RAM area. And the RAM SCR was strong enough to turn off the second SCR. This is a complicated theory, but if true, it would explain what we were seeing.

To fix the problem, we had to identify the initial SCR. We were never able to image the initial SCR, but we assumed that it had to be close to the second SCR which we had imaged. We studied the layout, and identified an N-Well in the IP that switched the EEPROM programming voltage from Vdd to the charge pump output, and back again. After a lot of spice runs, we decided that we could create a forward bias on N-Well if the load capacitance was large enough. And we have a very large load capacitance. Much larger than the IP was designed for. We had used the same IP to control an 8-bit register that we used to calibrate timing. In order to prove that switching could cause an SCR, we ran the IP at both elevated temperature and elevated voltages. And we were able to trigger an SCR. This confirmed that we knew how the SCR was being triggered.

The Fix

The IP was used to drive a row of 256 EEPROM cells. Since we already had wafers at contact, we didn’t want to make any changes to previous layers. We realized that we could modify the IP in metal and working with two adjacent IP cells, make one IP drive 512 bits, and the other drive just the N-Wells used to switch the supplies. Still, we didn’t want to wait on new silicon to prove we had fixed it. So, we developed a plan to disable all of the RAM except for two rows, and use FIB to implement the fix there. This worked, and there was no sign of an SCR, even at elevated temperatures and voltages.

Epilogue

We then revised our layout, and made new silicon. The fix worked perfectly. And the new parts worked over elevated temperatures and voltages with no sign of an SCR. Problem solved.

Since our move to Tekmos' new location our various Teams have started a more effective communication process using Microsoft Teams, a business communication platform that can be used from the desktop or smart phone.

Every weekday morning we have a Production Focus meeting with Team members from operations, assembly, quality, test floor, customer support and accounts payable/receivable. It has become an excellent way for each of us to start our day, relay our focus for the day, to share news and information, and to ask questions and clarify between departments about orders for customers.

Our Engineering Team also meets every morning to discuss the projects, share files they are working on and to update one another.

Tekmos Manufacturing Production Weekly meetings have become more effective in tracking part assembly, inventory and production.

Microsoft Teams is regularly used by all Tekmos Team members to speak directly to one another in face time, instant chat and along with group meets. It offers workspace chat and videoconferencing, file storage, and application integration making Tekmos communication across our departments much more efficient and a pleasant gathering space.

Tekmos Expands Partnerships with Design Engineering Companies

We have expanded our network with design center engineering companies, who provide the module, board or product solutions for OEMs.

Our value is in providing an ASIC solution and a multi chip packaging solution, which can include chips with mixed technologies into a final device that is fully tested.

If you work with ASIC companies and you have a need to build something unique or to combine multiple die into single package to save space, our program is designed to work as a partnership.

Feel free to contact Tekmos about the value Tekmos offers to enhance your relationship and profitability with customers.

Thank you for reading Tekmos Talks and helping us celebrate 20 plus years.

Sincerely,

Lynn Reed, President

Lynn Reed, President

Bringing Up a Reverse Engineered CPU

I have previously written about reverse engineering a CPU, and how we extract a Verilog netlist from a layout. Getting the netlist is only the half-way point. Now it must be verified.

The netlist of the CPU might have 50 to 100 connections, and since we extracted if from a physical layout, we don’t really know which signal is which. Loading the netlist into a Verilog simulator will generate errors on all of the inputs, since they will not be connected to anything. Most of the inputs can be identified by tracing the signals back to IO pads. If a line goes to the Reset pin, then it is probably reset. And we can identify the clock the same way. The databus is important to identify, though it can be difficult to determine which line is D0, and which line is D7. Other inputs can be tied off to a valid logic level, and identified later on.

An initial milestone is to get the circuit to compile correctly in the simulator. The simulator performs a check on the netlist, and if we can get to 0 nanoseconds, that means that all of the inputs have been identified, and there are no syntax errors in the netlist.

Now it is time to do something. Reset the part, start the clock, and see what happens. Initially, we put a NOP instruction on the databus, using a weak strength. This fixes any bus directionality problems.

The biggest problem we face at this stage is unknowns propagating throughout the simulation. Old designs frequently did not reset everyone. A divide-by-two in the clock circuit was a don’t care for which state it powered up in. In real life, it might not matter, but it certainly does matter in a logic simulation. So, we frequently have to add a global reset to all latches and flops that either don’t have a reset, or whose reset is not controlled by the reset pin.

Once the POR resets are dealt with, the next step is to look at those unknowns that are generated in the simulation. These can either be a result of a modeling issue that creates conflicts, or they can be a result of setup and hold violations. Once identified, both are easy to fix.

The next step is a quick look at all of the opcodes. Do they run? Do they appear to work? This check reveals gross errors that need to be fixed before the next level of checks.

This is also the time to modify the test bench so that the CPU is executing code out of a Verilog memory, with read and write control. We also have to set up scripts so that we can write an assembly language program, assemble it, and then translate the HEX file into a Verilog memory. This makes it very easy to generate stimulus for the CPU.

Now we go into a detailed check. At this level, we have a basic routine that initializes the processor, runs an opcode, and dumps the processor status so that we can see the results of the opcode, including any flags that might be set or cleared. We also want the opcode to have both set and cleared any flags, and to have taken and skipped any conditional branches. We make these checks self-checking, which reduces the amount of engineering time required to analyze the results. We also extract a test vector from these simulations, and use it to test the original part. This guarantees that we have created an exact copy.

Later, I will discuss design verification through the use of FPGA based emulators.

Thanks to Phil Buck, Chief Production Floor Technician, for organizing and cooking for Tekmos 1st Cook-out at our new location. Phil grilled hamburgers, french fries and hot dogs assisted by Cameron Combs, from IT. There was homemade macaroni & cheese and team members brought side dishes of pasta salad, green chile and hominy, jalapeno poppers, lemon bars and mandarin jello pudding.

	Phil Buck, Chief Cook & Organizer
	Cameron assists in cooking with Carole overseeing.
	Phil also honored the mothers of Tekmos with a lovely bouquet of flowers.

Tekmos Expands Partnerships with Design Engineering Companies

We have expanded our network with design center engineering companies, who provide the module, board or product solutions for OEMs.

Our value is in providing an ASIC solution and a multi chip packaging solution, which can include chips with mixed technologies into a final device that is fully tested.

If you work with ASIC companies and you have a need to build something unique or to combine multiple die into single package to save space, our program is designed to work as a partnership.

Feel free to contact Tekmos about the value Tekmos offers to enhance your relationship and profitability with customers.

Thank you for reading Tekmos Talks and helping us celebrate 20 plus years.

Sincerely,

Lynn Reed, President

Lynn Reed, President

The First Simulation

Near the end of the reverse engineering process, we wind up with a Verilog netlist and a library. The next step is to see if it works.

The first thing we do is to put the design into our Verilog simulator, and run it. Typically, there are a lot of issues preventing it from running. These are generally simple issues of typographical errors, or pin polarity issues on the input or output statements.

For processors, the next step is to see if it can execute an opcode. We typically use a NOP as our first test, since it is the simplest opcode. And that typically doesn’t work. So, we begin the process of debugging.

Almost every problem is a library problem, though these library problems are much more complex than just modeling a NAND gate. Instead, we are dealing with bidirectional transmission gates. And in many cases, these transmission gates are composed of a single NMOS transistor. I would like to give two examples of these problems.

Most micros contain a microcode ROM for instruction execution. These ROMS consists of arrays of NMOS transistors capable of pulling a bit line low. The bit line is forced high with a PMOS precharge circuit. The bit lines go through muxes to connect to the sense amp, and the precharge is located at the sense amp. This means that the muxes are actually bidirectional, sending a zero to the sense amp, and sending the precharge one back to the bit lines. Modern design techniques discourage bidirectional transmission gates, so there is not a direct solution. As an indirect solution, we add a weak1 pullup to the bit lines at the mux inputs. This emulates the precharge, and allows the microcode ROM to work.

In another interesting problem, we had a register containing latches with three D-inputs. The D inputs also served as the output, somewhat analogous to the operation of a 6-transistor static RAM cell. Whether a write or a read occurred was dependent on whether someone else was driving the databus at that time. This problem has two possible solutions. The first is to evaluate everyone who might be driving the databus at the time the latch is enabled, and generate a new signal that can be used to determine whether a read or write is occurring. A second solution is to study the circuit. In some cases, a write might only occur on some of the D inputs, while a read might occur on the other D inputs. In that case, the model can be constructed to reflect that.

As shown above, models frequently contain engineering judgements that can be wrong. We can check this by running spice against the whole design. The spice run times increase with circuit size, and a whole chip simulation can take a very long time. But we can do it for a limited number of clock cycles, and that is frequently enough to allow us to perform an analysis on the Verilog models and simulation.

Tekmos Expands Partnerships with Design Engineering Companies

Tekmos is an engineering/semiconductor chip company that specializes in chip development and turnkey chip solutions including all manufacturing and test.

We are expanding our network with design center engineering companies, who provide the module, board or product solutions for OEMs.

Our value is in providing an ASIC solution and a multi chip packaging solution, which can include chips with mixed technologies into a final device that is fully tested.

We have recreated many legacy processors as well as ASICs both mixed signal and digital.

We have also designed and made high temperature chips for oil services, defense, medical, industrial, consumer markets and are expanding into other areas including RAD Hard ASICs.

If you work with ASIC companies and you have a need to build something unique or to combine multiple die into single package to save space, our program is designed to work as a partnership.

Feel free to contact Tekmos about the value Tekmos offers to enhance your relationship and profitability with customers.

Congratulations

Kelsey Casto, and husband, Cy are happy to announce the birth of daughter, Cypress 5lb.7 oz., 18 inches

Kelsey is Director of Quality & Assembly Engineering at Tekmos

Thank you for reading Tekmos Talks and helping us celebrate 20 plus years.

Sincerely,

Lynn Reed, President

Lynn Reed, President

Libraries for Reverse Engineering

Tekmos is in the business of reverse engineering obsolete designs to support customers who need a continuing supply of these older parts. In these applications, it is necessary to make an identical replacement for the original part.

To make an identical replacement, we image the original part, convert that into a GDS database, and then extract a transistor level schematic. This transistor level schematic is converted into a gate level Verilog netlist, which is then simulated, verified, and eventually turned into an ASIC.

Tekmos already has libraries of gates, latches, and flops. And initially, we just mapped reverse engineered designs using our standard ASIC libraries. But this approach can introduce problems. For example, the Tekmos standard flip flop has reset connected to both the master and slave. In some of the designs that we have reverse engineered, the reset is only connected to the master, and not the slave. Replacing their flop with ours could introduce timing issues that might interfere with the operation of the overall chip.

We reviewed the approach, and decided that the best approach is to create new library cells that are identical to the ones in the original circuit. Or as identical as we can make it.

Some of the latches use cross coupled inverters that require a new value to be forced onto the inverters. This is generally a very bad idea in today’s technology, and there are logical equivalents that will perform the same function with the same timing without having the current spikes. Likewise, we see transmission gates used for logic functions and which can be replaced by more robust gates. But these are the exceptions, and we will create new cells that exactly match the originals for most cases.

Once the library has been created, we must verify it. If there is an error in the library, then it will cause errors in the Verilog simulations, and this can be very difficult to debug. The answer to this problem is to run spice on both the original library and on our implementation, and verify that they both behave in an identical manner. Combinational logic can be verified through a simple binary pattern. Latches and flops require a little more specialized pattern, in which we vary the flop contents with the set and clear controls.

In addition to the simulation library, we must also create a physical library for the place and route software. This is not a difficult task, but is time consuming. To verify this library, we create a dummy chip that contains all the cells, and then place and route it. Then we run DRC and LVS checks to make sure that the transistor level definition of our library matches the physical layout.

And that is how we create a library that provides a good foundation for the rest of the design.

Tekmos Expands Partnerships with Design Engineering Companies

Tekmos is an engineering/semiconductor chip company that specializes in chip development and turnkey chip solutions including all manufacturing and test.

We are expanding our network with design center engineering companies, who provide the module, board or product solutions for OEMs.

Our value is in providing an ASIC solution and a multi chip packaging solution, which can include chips with mixed technologies into a final device that is fully tested.

We have recreated many legacy processors as well as ASICs both mixed signal and digital.

We have also designed and made high temperature chips for oil services, defense, medical, industrial, consumer markets and are expanding into other areas including RAD Hard ASICs.

If you work with ASIC companies and you have a need to build something unique or to combine multiple die into single package to save space, our program is designed to work as a partnership.

Feel free to contact Tekmos about the value Tekmos offers to enhance your relationship and profitability with customers.

Remote Social Events for Team Building

As more of us work remote, fresh ideas are needed to keep the work Team connected.

Here are some virtual ways to have fun worth checking out:

• Go Game – virtual game show
• Let’s Roam – virtual team trivia event
• The Escape Game – virtual escape room

Thank you for reading Tekmos Talks and helping us celebrate 20 plus years.

Sincerely,

Lynn Reed, President

Lynn Reed, President

Tekmos is Moving

After 6 years at our present location in east Austin, Tekmos is moving to new facilities in west Austin. And we are taking advantage of the move to address the new normal for professional employees. Before the Covid pandemic, we had perhaps 10% of the company working remotely. During the initial lock-down, this percentage went up to 75%, though it has drifted back down to about 50%. We believe that there has been a fundamental change in office organization, and that working from home is not a temporary reaction to the pandemic, but instead a permanent change in the way of doing business. We choose to embrace this change.

The new facilities are mainly for manufacturing. Testing, baking, tape and reeling, and shipping must be done on-site. On the other hand, professionals will work remotely, reducing the need for on-site offices and cubes.

There have been problems associated with half of the company working remotely, with the main one being communications, both external and internal. Externally, the traditional phone system doesn’t work well when there is no one around to answer the phone. So, we are replacing it with a VOIP based system. As a side note, switching to a VOIP system has led to interesting discussions about who really needs a phone.

These days, almost all external customer communications are through video calls. The only calls coming in through the land line are an occasional new customer query, an occasional finance question, and with the clear majority of incoming calls being spam. Does an engineer need a VOIP license, or will he be equally served by transferring the occasional call to him? We decided to drop engineering and most manufacturing from the system, and will use call forwarding to cell phones for those few legitimate calls.

The big communications issue is internal communications, which is mostly resolved with IT solutions. We have provided cameras and headsets, and switched to Microsoft Teams for meetings and informal conversations. That is working well, with most people having adapted to using it as the main means of communication. We are going to switch to a cloud based Microsoft mail server to allow for a tighter integration of email with Teams. File sharing is more difficult, since we are no longer on the same network. We solve this by doing a two-step transfer, using the company servers as an intermediate step. Accounting is also affected, and we are going to switch to a cloud based system.

We will have office space available at our new facilities when in person collaboration is required. For example, it is impossible to remotely use a scope on a chip. Finally, we are going to have a weekly company lunch, which will bring everyone together and make it easier to communicate.

With professionals gradually moving to working out of their houses, there is no exact move date for them, and the transition should be seamless.

Manufacturing will be shut down for about 3 days during the move. This will not affect delivery schedules. The exact move date has not been set, but will be in early March.

Tekmos Phone 512-342-9871 & website www.tekmos.com will remain the same.

Notifications will be sent to all customers and vendors with our New Address and the effective date.

Remaining Proactive in the New Work Paradigm

Being effective in the workplace means so much more now. The COVID-19 pandemic has changed the work paradigm permanently. Workers around the world have had to adjust to that change wearing masks, social distancing, communicating specifically, succinctly, and often, to working remote part, or all the time, adding stress.

The 7 Habits of Highly Effective People by Stephen Covey published over 30 years ago continues as a guide for educators, HR trainers and military alike. School systems use the 7 Habits to guide young people in making better choices for the future; to work together as well as independent. In today’s business climate, the 7 Habits are perhaps more essential.

The 7 Habits break down into three sections: Independence, Interdependence and Continual Improvement. We will focus on the 1st section and 1st Habit- Being Proactive, and continue with a new habit in future articles.

Independence begins with Being Proactive: Take responsibility for your reaction to your experiences, take the initiative to respond positively, and improve the situation. Recognize your Circle of Influence and Circle of Concern. Focus your responses and initiates on the center of your influence and constantly work to expand it. Don't sit and wait in a reactive mode, waiting for problems to happen (Circle of Concern) before taking action.

People with proactive attitudes are typically energetic, good planners, alert to signs of problems that might arise, and they are creative in coming up with ways to solve those problems. A strong positive business culture is created with proactive people.

The Circle of Influence for Tekmos relate to specific jobs such as Test Floor, Operations, Assembly, Quality Control, Administrative, Customer Support, Sales, and Design Engineering. The Circle of Concern includes the wide range of everything in the world that is important to each individual. When it comes to the job, a worker will use their Circle of Concern to apply to that job.

Some key points for leaders to create proactive teams in the workplace more specifically with remote teams are:

1. Build awareness of expectations. Conversations about what effective performance looks and sounds like are often found missing. No team member knows what they don’t know, so regular communication from leaders is key.
2. Understand individual motivators. Great performers are always people who have aligned their work to their values so that they are passionate about what they are doing. Great leaders align the values of work to their team.
3. Capitalize on the strengths of each team member. When hiring it’s important to discuss strengths and development areas. Always try to align people’s roles to their natural talents and interests.
4. Support team members in being accountable. Communicate the measurable results expected, and get a commitment for specific action steps and time frames. Remember that you must role model and reward accountability to get it from your team.
5. Provide real feedback on their performance. Performance feedback works and is appreciated when it is done often, and in the context of specific accountable actions. Once per year discussions, only when there is a problem, don’t work.
6. Celebrate successes and even small steps. Always affirm and reward team members, and criticize infrequently. Experts say it takes five positive interactions to dilute one negative if we want the relationship to thrive. Create a positive emotional wake.

At Tekmos we have weekly start-off meetings on Mondays, daily engineer Team meetings, a Manufacturing/Production meeting on Wednesdays and numerous Team Channels and meetings depending on what division from HR, AP/AR, Engineering, Sales/Marketing, Assembly and more.

Tekmos had its Management Review the final week of January. The purpose of Management Review is to review and evaluate the effectiveness of your Management System, helping you to determine its continued suitability and adequacy. As mentioned earlier, the business/work paradigm has changed permanently, and those recent trends need to be adapted. Today more than ever, workers are managing with a focus on good communication and staying Proactive will help keep the cohesion within the company.

Next time we will talk about Habit #2 Begin with the End in Mind.

Remote Social Events for Team Building

As more of us work remote, fresh ideas are needed to keep the work Team connected.

Here are some virtual ways to have fun worth checking out:

• Happy Hour Box – virtual happy hour
• Go Game – virtual game show
• City Brew Tours – virtual beer & cheese tasting
• Let’s Roam – virtual team trivia event
• The Escape Game – virtual escape room

from Snack Nation

Thank you for reading Tekmos Talks and helping us celebrate 20 plus years.

Sincerely,

Lynn Reed, President

Lynn Reed, President

The Design of a Masked Rom

In this article, I would like to cover the choices behind making a masked ROM, and the design of the ROM array.

The first question that should be asked is why would anyone ever design a masked ROM when you have flash? It is a good question, and we have two answers. The first is that this ROM is being designed for high temperature applications, and flash memories lose their data at high temperature. Flash memories use stored charge, which will leak away over time. The leakage rate is a function of temperature, and roughly doubles with every 10C rise in temperature. A 10-year life at 125C reduces to a matter of hours at 275C. And that is if the flash is built on a fully depleted SOI CMOS process, which most are not. This reduction in flash lifetime can be partially addressed by frequent refresh operations.

A second reason for considering a masked ROM is that many processes do not support the flash technology, whereas all processes can be used to make a masked ROM.

Once the decision has been made to make a masked ROM, the next choice is the architecture of the ROM array. There are two options: NAND and NOR. NAND has better density, but is slower, and uses more power. NOR has worst density, but is faster and uses less power. In the past, all our ROMs have used the NAND architecture. This time, we opted to use the NOR architecture. At high temperature, everything runs slower. In computer systems, the memory speed is usually the bottleneck, and so it makes sense to design the ROM for maximum speed. Our initial design goal is to have a sub 100 ns access time at 300C.

The design of the ROM array is about as simple as possible. Each ROM bit consists of a single N-channel transistor. The source is tied to ground, the gate is connected to the word line, and the drain is connected to the bit lines through the programmable contact. If there is a contact, the bit line goes to zero. If there is no contact, the bit line stays as a one.

The poly word line resembles a transmission line, and it can take the signal a long time to go from one end to the other. We are using a special high temperature process that does not support salicide. Thus, the poly is quite resistive. We address that by running a metal line over the poly, and connect it to the poly every 8 bits. This greatly improves the ROM speed for those bits located the furthest away from the word line drivers.

The next thing that we should worry about is the impedance of the ground lines. This is aggravated by the use of Tungsten as an interconnect metal. We have to use tungsten because aluminum has metal migration problems at elevated temperatures. To lower the ground impedance, we run perpendicular ground lines every 64-bit lines that convert the ground line from a single stripe into a grid. This allows every ground line in the array to help lower the impedance.

We do have to add additional bits. The initial ROM was an array of 512 rows by 512 columns, for a total of 256K bits. We will group every 8 bit lines together to produce a single output bit. This produces a 64-bit word. To improve reliability, we are adding ECC to the ROM, which will require 7 more output bits, or 56 more bit lines. And we need to add one additional bit line which is always programmed to provide a reference for the self-timing. This will be discussed later.

At this point, I have an array with 512 rows and 569 columns. I will discuss the word lines and their decodes in a future article.

Tekmos Remote Work Best Practices

Do people love remote work? For most, including at Tekmos, they do, and it’s mainly the flexibility. Travel and commute are reduced including the cost of both. There is a reduction of distractions. The ability to travel and live anywhere, including outside of major cities offers workers the ability to be closer to family. A big plus is often an increase in productivity.

At Tekmos we use Microsoft Teams to share, communicate by division and as a company. While we use our company email to share across our divisions, and telephone calls, Microsoft Teams allows us to see, hear, share, and speak to one another as a group or one on one using cameras, microphones and headsets. Tekmos' communication skills have improved greatly which has increased cohesiveness among team members.

US Census Bureau and the Bureau of Labor Statistics showed that 4.7 million people, which make about 3.4% of the US workforce, were already working remotely before the novel coronavirus took the world by storm. Regular work-at-home has grown 173% since 2005, 11% faster than the rest of the workforce (which grew 15%) and nearly 47x faster than the self-employed population (which grew by 4%) (Global Workplace Analytics’ analysis of 2018 ACS data).

What is the most important issue for remote working? Communication tops the list, with 27% of people mentioning it as their #1 challenge. Remote work makes it harder to read body language, hear what people are saying, ask follow up questions in the hallway, or quickly ask a coworker for clarification at their desk. Lacking social interaction and isolation are close behind. Again, Microsoft Teams offers the ability to see, hear and interact with coworkers.

Best Practices to thrive as a remote worker

Practice good meeting etiquette. Using cameras at all desks gives opportunities to keep people engaged in the conversation as we all know we tend to “check out” and find other things to engage in. Working on other things during a meeting can be distracting to others and shows a lack of interest in the task at hand.

What makes you most productive? Some people work deep in the mornings and light work later in the day. Taking breaks are important to splitting up the day. It’s easy to reach burn out if you do not break up the day.

Prioritize documentation and clear communication. Some of us work in different time zones than other co-workers. The use of Microsoft Teams gives co workers chat, file share and video conferencing immediately…like walking into an office for a quick question or approval.

Create boundaries between work and life. Those who have already worked remote before Covid know how important it is to “unplug” from the day. A good plan is to have a work space that is designated for just that so you can walk away and close the door.

Keep yourself visible at work. Communicating daily with co-workers keeps remote workers visible to one another. Responding to questions or concerns from a co-worker promptly helps keep that cohesion for success on projects.

Connect often with teammates. In the new year Tekmos plans to have weekly lunch meetings with team members at a local restaurant. Currently we have Monday morning team meets to start out the week, manufacturing meetings on Wednesdays to discuss production, and plans to have at least a week wrap up.

Build in accountability. Create blocks on calendars for work and breaks. Make a task list and check off as you go. Share your schedule and updates so that co-workers know what you are doing.

Brittany Combs, Office Manager

What brought you to Tekmos?

Having a background in Oil & Gas, I was drawn to the Tech sector as a new opportunity to diversify my knowledge and resume. Tekmos was an easy decision when I considered the company culture, environment and stability.

What are your responsibilities here at Tekmos?

As the Office Manager, I handle the general tasks of daily mail, coordinating Corporate Events and meetings as well as Accounts Payable, Accounts Receivable and HR duties.

What are your favorite tasks or projects to work on here at Tekmos?

Although I am in my infancy here at Tekmos and learning every day, my favorite task thus far is account reconciliation. I love a good challenge and have always enjoyed puzzles.

Please tell us about your professional and educational background. Do you have any hobbies?

I am a Culinary graduate and was a Chef for many years before transitioning into back office. I found a niche (almost accidentally) in Accounting and have been loyal ever since.

In my free time, I enjoy live music, kayaking/ paddle boarding Lady Bird Lake, cooking and entertaining, anything involving my puppy, and when afforded the time, I dabble in painting, mostly oils and acrylics.

Thank you for reading Tekmos Talks and helping us celebrate 20 plus years.

Sincerely,

Lynn Reed, President