ASIC Replacements

The semiconductor industry is volatile, and many ASIC manufacturers are either no longer around, or are not offering ASICs any more.  So what do you do if you need more parts?  You come to Tekmos.

And when you come, bring the original vendor signoff documentation package and a couple of reference parts.  That is all we need.

How We Do It

Every chip is different, and a lot depends on what is contained in the original design documentation.  If it is RTL, HDL, or VHDL, we can synthesize it into the Tekmos library.  More typically, we start from a post-route, gate level netlist.

We then recreate the simulations using the original simulations as a reference.  This provides the confidence that we have implemented the netlist correctly.  We will also run fault coverage on the vectors to make sure that they are effectively exercising the circuit.  We like 95% fault coverage, though we accept original vectors with coverages as low as 85%.

Sanity Checks

One of our steps is to extract test vectors from the simulations, and use them to test the original parts you have supplied.  This provides confidence that the design package matches the silicon.  It is rare, but we have had cases where there was another revision that occurred after the provided design package was released.  We also characterize the I/O, to determine the actual I/O characteristics.  We want our design to match the original part’s performance instead of the paper specifications.

Layout and Post Route

Once the simulations match the silicon, it is time to implement the design.  The first step is layout.  The netlist is flattened, load violations are fixed, clock trees inserted, and the circuit is placed and routed.  Typically, the routing introduces additional load violations.  These are fixed, the circuit is re-routed, and the post-route simulations are re-run.  Eventually, the designer is satisfied with the post route simulations, and we tape out.

Wafers

The choice of which fab to target depends on what we are making.  We use a German fab for most of our digital gate arrays.  An ITAR design usually requires a U.S. fab, and a high analog content part may require a third fab.  Whichever fab we use, it takes about 1 week for the masks, and another 2 weeks for the processing.  This is where our gate array technology can really cut down on the fab cycle times.  Often, wafers have already been processed, waiting for the design specific layers to be made. Even if we need a new base array, wafers can be started during the design cycle so that they are ready and waiting for the programming layers when the design is complete.

Assembly

When the wafers are complete, they need to be assembled.  The choice of assembler is dependent on the package type.  Since Tekmos makes parts in many different package types, we use a number of different assemblers in the United States and Asia.

Testing and Prototype Delivery

Tekmos does almost all of its testing in house.  The prototypes are tested with the same programs used to verify the original silicon.  Then we give them a 1 to 2 day dehydration bake (thicker packages need a longer bake) and ship them to the customer.

Manufacturing

The initial prototype lot can frequently serve as the initial production material as well.  Production quantities are usually available in 4 weeks, and unlimited quantities in 8 weeks.

And that is how we do it.

Former ASIC Manufacturers

Here is a list of former ASIC manufacturers for which Tekmos offers replacements.  This list is by no means all inclusive.