TK17LV040 Serial Configuration Memory

General Description

The TK17LV000 series of serial configuration memories provide an easy-to-use, cost-effective configuration memory for FPGAs. Capable of a 30 MHz data load rate, the TK17LV000 series provides a new level of support for large FPGAs, while retaining backwards compatibility with existing smaller configuration memories and PC board layouts.

The TK17LV000 series supports serial loading for most Xilinx ®, Atmel ®, Altera ® and Lucent/Agere ® FPGAs. Multiple FPGAs in series may be configured by a single TK17LV000 series part. Large FPGAs needing in excess of 8 Mb may be supported by cascading multiple TK17LV000 series parts. Conversely, existing 2 Mb or smaller parts, in stand-alone or cascade mode, can be replaced by the TL17LV000 series without modifying the existing circuit board. And the high speed capability reduces the FPGA configuration time for advanced FPGAs.

The TK17LV000 series supports a number of user programmable options. The user may set the polarity on the RESET / OE pin. The user may also program the power-on-reset delay for the READY signal, which signifies the presence of a valid power level.

The choice of which chip enable input to use is user programmable, allowing the TK17LV000 to be compatible with existing applications using the Atmel ® “A” series. The TK17LV000 also supports both the sourcing of the DCLK clock signal and control of the DCLK frequency.

The TK17LV000 series incorporates a sophisticated approach to In-System Programming that supports multiple cascaded devices while eliminating the need for external support circuitry.

The TK17LV000 series can be programmed in system by software, out of the system using industry standard programmers, or purchased pre- programmed by the factory.

Features 

Programmable delay in the READY output insures system power supplies have stabilized.

Supports DCLK clock generation and CS_N (versus CE_N) pin assignment.