Process Technologies

Advanced Technologies, Without the Cost

28nm, 45nm, 65nm

The mask costs associated with advanced technologies are expensive. And the expense roughly doubles with each process generation. That fact has meant that the minimum volume necessary to justify an ASIC has also doubled with each generation. And because many applications do not need a million pieces, the overall ASIC business has declined, and many ASIC vendors are no longer around.

The Tekmos approach to this problem is to make use of the MPW (Multi-Project-Wafers) runs at the leading foundries for manufacturing purposes, instead of for prototypes. A MPW run will reduce the mask cost by a factor of N, where N depends on the die size as a percentage of a 20 x 20 mm area. The number of raw die on a wafer is limited to about 100 on a 300 mm wafer. A subsequent production order of 25 wafers will provide about 2500 parts.

Trade-Offs

Because of the way a MPW is configured, the die cost is not related to the die size.  Instead it is a function of the number of “slots” that are on the MPW mask set.  So we have the option of purchasing multiple slots on a MPW run, increasing the NRE, but lowering the unit cost. 

Further Savings Through Merges

Tekmos can also do design merges, which allows us to put multiple designs on a die.  This does not affect the manufacturing cost, but it will provide NRE savings.

110nm

This is a 130nm process that has been optically shrunk to 110nm. With a 175K gates/mm2 density, and flash support, this process generates superior speed performance while still possessing reasonable mask costs.

180nm

This is our most cost effective process, with 64K gates/mm2 density, and very low mask costs. The process supports up to 200 MHz clock rates, and 1.25 GHz SERDES operation. 

0.35u, 5V

This is our main 5V process, using a triple metal, dual oxide technology. We have 4 different gate arrays in this process, with each supporting 5 volt operation and each containing smaller analog arrays for mixed signal applications. All of these arrays have been designed to support 4M Flash memories in a stacked die configuration.

Tekmos uses a gate array approach to our ASIC design. A new design is not required to use an existing gate array. However, if it can be used, then there can be substantial NRE saving and additional volume flexibility.

0.6u, With NVM

This ASIC process has excellent analog features and a 5 volt NVM capability.  We use it extensively for our 68XX microcontrollers.  As with the 0.35u process, we have existing gate arrays than that be used to lower the overall NRE charges.

An interesting variant of this process uses the medium voltage transistors of the EEPROM everywhere.  This produces a circuit capable of 10 volt operation (or +/- 5 volt) .

1.0u SOI

This is the process that we use for high temperature (250C) operation.  It uses tungsten interconnect, and the SOI transistors do not have leaky junctions because they don’t have junctions.  We have our basic technology libraries mapped into this process, and so we can map any existing digital design and some analog designs into this process.

The 1.0u process is an older process, and that limits the upper operating frequencies to the 20 MHz range at 5 volts.    

Stacked Die

There are times when there is not a good match between an application and a technology. For example, a low volume microcontroller may require a large amount of flash. The flash requires a modern low voltage process with expensive masks, and the controller can be most economically made with an older process with less expensive masks.

One solution is to stack two separate die in a single package. Sometimes called 2.5D integrated circuits, this is an excellent way to combine disparate technologies. Tekmos uses this approach on all of our flash-based microcontrollers. It is also a good way to combine precision analog circuits with digital or other custom analog circuitry.