FPGA Conversions

An FPGA based design can be converted into an ASIC, which can then be used as a drop-in replacement.  FPGA conversions can be used as a cost reduction, for power reduction, to save board space, or as a solution to the problems of FPGA obsolescence.

Design Files and Simulations

An FPGA conversion begins with the original design files.  These can be the RTL used to generate the design, or the gate level FPGA netlist.  Tekmos converts these files into the Tekmos library.  We need to run simulations to make sure that the design has been correctly converted.  Ideally, there are existing simulations that we can use.  If not, then we will have to write them.  We have ATPG tools and can do a scan insertion.  But while this is fine for production, it does not confirm the correct operation of the design.

When our design is done, we extract a test vector from the simulations.  Then we program an FPGA with the customer programming data, and run our simulations against it.  This confirms that our design works in the same manner as the original FPGA.  It also confirms that we have been given the correct design files.  The documentation on old FPGA designs may not have been kept up to date, and we need to make sure we are making the current design.

Programming Emulation

Our ASIC replacement can be ready for operation as soon as power is supplied.  However, in some cases, it is desirable for our part to emulate the programming process.  There could be existing firmware that needs to successfully load the FPGA before normal operation can begin. In these cases, Tekmos can design a programming emulator into our design.  We don’t actually use the data, but we can trick the rest of the system into believing that we do.

IP

Ideally, the customer owns their designs.  But some customers use “free” IP from the FPGA manufacturers.  That IP is free only as long as the design is implemented in the vendor’s FPGA.  When the design is transferred to an ASIC, then the IP will have to be designed or purchased from a 3rd party.  There are a lot of IP vendors in the world, and each case is different, with a different solution.  Still, the customer has to have the rights to their own design before we can make it.

Power Reduction

An ASIC will reduce the power consumption of an FPGA based circuit typically by a factor of 3-6.  Why?  The main reason is that the ASIC uses fewer transistors to implement a logic function.  The logic blocks in an FPGA are actually small ROMs.  And being ROMs, they have an address decode, and some sort of output circuit.  In an ASIC, we just implement the logic gate.  The total power consumption is directly related to the number of transistors switching, so if we reduce the number of transistors that switch, we reduce the power.

Another source of power reduction is more subtle.  Because an ASIC uses fewer transistors than an FPGA, it can be implemented in an older technology and still achieve the same performance level obtained in the FPGA.  And while older technologies have larger transistors, and thus draw more operating power, this can be offset by the reduction in leakage found in the latest technologies.

Packaging

The customer has a choice.  We can match the original FPGA package, or we can provide the ASIC in a more appropriate package.  Many FPGAs have a high pin count.  And there are applications that just don’t require that many pins.  In these cases, we can provide the ASIC in a smaller package.  Package cost is proportional to the number of pins, so reducing the package size can result in cost savings.

Design Options

An FPGA conversion is not limited to just the contents of the FPGA.  Additional circuitry can be added to the design or included in the package through a stacked die approach.

ITAR

We can implement ITAR designs with a full US product flow. 

Prototypes and Production

When the design is complete, we tape out, make masks, make wafers, and then assemble and test prototypes.  We typically provide 10 prototypes, with production quantities available in two to four weeks after prototype approval.