TK17LV040 - FPGA Serial Configuration Memory
Features
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Programmable delay in the READY output insures system power supplies have stabilized.
Supports DCLK clock generation and CS_N (versus CE_N) pin assignment.
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Main Office
Tekmos, Inc.
14121 Highway 290 West
Building #15
Austin, TX 78737
Phone: (512) 342-9871