Tekmos' Blog

We recently had a requirement to test some parts at 150C.  In order to do that, we use a temperature forcing probe.  This is a washing machine size box with an arm that holds a test chamber.  The machine can force hot and cold air into the test chamber, and allow us to raise the temperature to any desired value.  It is not fast, and can take a minute to reach the final temperature, but it works.

One problem is that the bottom of the temperature chamber is open, and so if we don’t do anything, we will also raise our tester to 150C.  Testers are finicky, and would prefer to be at 25C.  In order to prevent problems, we need a thermal insulator to put around the part.  They sell a rubber sheet that is pretty good, but rather expensive.  And we needed a solution that day.  So we went over to Bed, Bath and Beyond, and bought silicon cooking mats.  These were trimmed to the desired size, and augmented with a lower layer of insulator, and this worked fine.

We have a future requirement for testing parts at 175C.  In this case, we are beginning to exceed the temperature range of our probe, and so we will build an extension cable, and test parts directly in one of our ovens.  The silicon mats won’t be good for us, but the Bed Bath and Beyond oven mitts will definitely be useful.

One of the biggest challenges we face in the replacement of obsolete parts is replacing the obsolete packages.  We can re-create designs and implement them in new technologies, but we don't have the same flexibility for the packages.  And while newer packages are easily available, there may be engineering or regulatory reasons why we cannot change the existing PC board to accommodate a newer package.

If a given package is not offered by one of our main assembly vendors, we first search to see if anyone else in the world offers it.  The initial step is to look at their web sites and see what they offer.  This is harder than it seems.  The web sites may not be in English, and they may not be updated.  We have frequently inquired, only to find that a specific package is no longer offered.  The contact information is also challenging.  And a given vendor may not be interested in what is for them a very small piece of business.

The cost is frequently higher from smaller vendors.  Many have optimized their business around military work, and that can result in an increase of $20 per part to cover the packaging alone.

Some packages are just not obtainable.  In those cases, we have to build an adapter card.  We have used adapter cards for 56-pin SDIPs, 84-pin PGAs, and 84- and 132-pin BQFPs.   

We have a R&D program underway that is looking into two different replacements for PLCC packages.  One involves a special adapter card. The other uses a special LGA (Land Grid Array) package with a footprint created to fit the existing PLCC footprint.  In both cases, our first step is to check the reliability of the cards.  We have created parts with pairs of pins shorted inside of the package.   This allows us to create PC boards that are a huge continuity chain.  We will subject these boards to thermal cycling, and see if any of the cards develop opens.   

A normal gate array prototype cycle takes about 8 weeks.  There is a week to make masks, 3 weeks for wafer processing, another 2 weeks for assembly, a week for test and bake, and a final week that taken by shipping between the various stages.

Sometimes, 8 weeks is too long, particularly if a customer faces a lines-down situation.  In these cases, expedites can help to reduce the total cycle to under 3 weeks.

The first part of an expedite is to pay the wafer fab to turn the lot into a hot lot (or bullet lot).  This will reduce the fab and mask time from 4 weeks to about 10 days.

Expediting the assembly is more complicated.  Most overseas manufacturers are pretty efficient, and an expedite will reduce their cycle time from two weeks to about 1 week.  This is dependent on their capacity at any given time.

 Domestic assemblers are an option, but they must have the tooling for the specific package you need.  With expedites, that can usually turn a package in 2 to 3 days.  And there is an additional time savings to be had from the reduced shipping times.

The newer fabrication technologies provide substantial performance advantages of increased speed and reduced power.  They also provide the disadvantage of increased mask cost.  And this makes many opportunities with lower volumes uneconomical.

But there is a way around the mask costs.  Most foundries offer shuttle runs.  A shuttle run divides the mask into multiple regions, and puts a different customer's design into each region.  The mask cost is shared by all of the customers, and is proportional to the area used by each design.  The fab then runs a lot of wafers with the shuttle mask set.  When the run is completed, the wafer is divided up, and each customer receives a small number of die. While the individual die is expensive, the total cost is much less than using a dedicated mask set and wafer run.  Additional wafers can be run using the same mask set, allowing small to medium volumes.   

The economics are interesting.  Assume a $500K total mask set charge, and a $4000 wafer cost.  A 5x5 mm die represents 1/16th of the mask area, and would appear 165 times on a 300 mm shuttle wafer.  The mask charge is reduced from $500K to $32K, while the die cost rises from $1.50 to $24.00.  This makes the volume breakeven point for buying a full mask set be 20K units.  There are a lot of opportunities that have volumes much less than 20K units.

The economic feasibility exists.  We now have to productize it in order to offer low cost ASICs in the 65 to 180 nm range.  And that will be the topic for a future newsletter.   

I attended the HiTEC 2012 (High Temperature Electronics Conference) in May.  The conference alternates every other year between the UK and Albuquerque.  While listening to the paper presentations is always educational, the real value in conferences is the opportunity to talk with prospective customers, and to visit the exhibit area and see which companies are exhibiting and what products they are featuring.

The amount of Federal R&D support has been dramatically reduced over the past few years, and that was reflected in a reduction in the amount of research papers.  This was partially made up with an increase in papers from the larger semiconductor companies.  Both TI and Analog Devices are making a renewed effort to offer high temperature products.  There were more companies exhibiting than two years ago, and there were more semiconductor products available.

We must always question how Tekmos compares to the competition in our high temperature offerings, and I think that we are doing well. It appears that most >200C chips are still produced internally by the users themselves, and that we are the only ones offering high temperature ASICs to run at 250°. Tekmos has achieved "tape out" on a high temperature ASIC designed to run at 250° C.

I also note that our internal developmental work is on a par with the published papers.  And I think we should expand our efforts and publish our own results in a future conference.

Albuquerque is a nice city, and I always enjoy visiting there.  The presence of Sandia Peak over looking the city adds a natural backdrop that is missing from many other cities.