Tekmos' Blog

Tekmos offers customers the ability to have their ASIC or customer specific designs created and manufactured in the United States. This is typically important for companies that require ITAR compliance in their market.

The ability to design a unique customer specific part can provide competitive advantages and exceptional protection of confidential intellectual property.

Tekmos performs all design work in our Austin, Texas technology lab.

We can then have masks created, wafers fabricated and assembled with our partners in their US facilities. Tekmos then tests every part in our Austin test facility before shipment to customers. A customer specific design is essential when the application requires functions that are not readily available from standard products or when IP must be protected under the ITAR compliance rules.

Tekmos can build a wide range of devices including microprocessors, digital, analog, extended voltage ranges and supports extended temperature from -55ºC to as high as 250ºC. Our engineers are very skilled at including existing IP already developed to provide a very fast lead-time for prototypes and production units.

Production ASIC technology nodes range from 16nm up to 600nm, and the 10nm and 7nm nodes are nearing production status. With each decreasing technology node, in rough terms, the NRE doubles, the logic density doubles, and the wafer cost increases by ~25%. Going to a more advanced note can result in a cost savings as long as the volume compensates for the increased NREs.

There are two items that work against migrating to a more advanced node. The first is the anticipated production volume. Economically speaking, this can be phrased as how many production parts does it take before the unit cost savings equals the increase in NRE, and how long will it take to reach the breakeven point?

How long it takes to reach that breakeven point is important. A node selection that breaks even in 5 years is not economical. A project that breaks even in a few months is a no-brainer. Typically, an ASIC node selection needs to breakeven in under a year, with a 6 to 9 month period being ideal.

A second point to consider is that an increase in logic density at a given node does not always result in a lower cost die. A die consists of core logic that is surrounded by a pad ring that consists of the input / output buffers, the power bussing, and the scribe line (the space required to allow the die to be cut from the wafer). The I/O buffers have a minimum size that is necessary to withstand ESD damage. The pads have a minimum size because of assembly constraints. And together, this produces a pad ring that does not change size with differing technologies.

Consider the case of a 256 pin circuit with a 50u pad pitch. This die will be a minimum of 3.5 mm / side, and have a core area of 6.25mm². This tables show how many gates can be put into that 6.25 mm² space. So if a design has less than 400,000 gates, and if the 180 nm node will support the speed requirements, then there is no reason to use a smaller technology node.

There are many technology nodes available today, ranging from the most advanced 16 nm up through 1 u. So which one should you use for your ASIC? The answer depends on a combination of circuit size, speed requirements, and production volumes.

The biggest downside for the advanced technology nodes is the cost of the masks necessary to fabricate the wafers. The mask cost tends to double for each successive technology node, and is in the millions of dollars for the most advanced nodes. The manufacturing cycle is also longer for the more advanced nodes.

The advanced nodes offer greater circuit density, with the density roughly doubling for each node. This reduces the manufacturing costs, but are the savings worth the extra NRE charges?

And there is the issue of circuit speed. A DDR4 interface needs at least 65 nm for implementation. A PCIe G3 needs 28 nm. And a mixed signal part can be successfully implemented at 180nm or less. The application sets a lower limit on the technology node.

So how do you determine the optimum node? First, let the speed set the lower limit. And trade off the manufacturing cost versus the NRE cost for your anticipated volume. As a rough rule of thumb, the manufacturing savings should pay for the increase in NRE charges within 6 months.

2013 is almost over, and we have had a good year.  At a minimum, our sales have doubled this year, and we have a good chance to triple sales for next year.

Double and triple digit growths are worthy, but they bring with them new challenges to address that we here at Tekmos enjoy taking on.  You can handle a little growth by working more efficiently and by just working a little harder. Tripling our growth means addressing the bigger picture.

Tekmos’ solution is to change the definition of some jobs, and to delegate into a new level of management. The process of identifying our growth opportunities means concentrating on our products, services, customers, channels and geographic areas that generate the largest proportion of revenue and profits.

An evaluation of the overall performance of Tekmos is ongoing and involves measuring and benchmarking profitability, rate of revenue growth and our reputation with our customers. This year we successfully entered new markets, created new products that appeal to that new customer base and as always, Tekmos provides an outstanding level of customer service. We will continue on that path for 2014.

We are going to make a cautious bet on growth.  We will grow, and be a leader in the semiconductor industry as we have already demonstrated with our high temperature ASICs and Microprocessors for extreme 

Last month I took a trip to Japan to meet with some of our customers.  We have started selling ASIC replacements in Japan.  Many Japanese customers had purchased their ASICs from the major Japanese semiconductor vendors.  And now, those same vendors have been End-Of-Life-ing their products.  This creates the same sort of demand for replacements ASICs as we have seen elsewhere.  And now that we have a partner in Solekia, it is a good time to increase our sales in Japan.

I have been to Japan once before, 25 years ago, on a trip to Osaka.  I had ventured into their subways, and backed right out again for fear of getting terribly lost because I couldn’t read the signs.  The fear never left me, and now I was going to have to face it on this trip.  Fortunately, I have my smart phone, with its’ built in GPS.  This allows me to know where I am, even if I can’t read a station sign.

As is frequently the case, the fear is worse than the reality.  While most station signs were in Japanese, there was always an English sign somewhere, and that was enough to get me to my destination.  My hosts were also concerned that I might disappear before an important meeting, so they met me at the hotel each morning to insure that I did arrive where I was supposed to be, and at the correct time.  I tried to go totally native, but I do admit to a strange longing every time I passed a McDonalds.

We visited two ASIC customers during my trip to Japan.  One was located in Tokyo, while the other was perhaps 200 miles north of Tokyo.  I rode the bullet train there at a speed of 150 mph, which was faster than I had been on a train before, with my old record being 100 mph in the UK.  It was a nice trip, and I enjoyed looking out the window at the countryside.

That area of Japan was near the reactors that were damaged in the Sendai earthquake, and some of the towns had erected public displays of the current Geiger counter readings.  That was interesting, though the readings were just ambient on a sunny day.