There are many technology nodes available today, ranging from the most advanced 16 nm up through 1 u. So which one should you use for your ASIC? The answer depends on a combination of circuit size, speed requirements, and production volumes.
The biggest downside for the advanced technology nodes is the cost of the masks necessary to fabricate the wafers. The mask cost tends to double for each successive technology node, and is in the millions of dollars for the most advanced nodes. The manufacturing cycle is also longer for the more advanced nodes.
The advanced nodes offer greater circuit density, with the density roughly doubling for each node. This reduces the manufacturing costs, but are the savings worth the extra NRE charges?
And there is the issue of circuit speed. A DDR4 interface needs at least 65 nm for implementation. A PCIe G3 needs 28 nm. And a mixed signal part can be successfully implemented at 180nm or less. The application sets a lower limit on the technology node.
So how do you determine the optimum node? First, let the speed set the lower limit. And trade off the manufacturing cost versus the NRE cost for your anticipated volume. As a rough rule of thumb, the manufacturing savings should pay for the increase in NRE charges within 6 months.