Explaining NRE's

To make an ASIC, you have to pay a non-recurring engineering cost (NRE). We’re going to talk about what makes up an NRE.

Masks and Wafers

A significant portion of the NRE is made up of the mask and wafer charges. This portion of the NRE can vary from a low of $30K to a high of $150K at 110 nm, and much higher for smaller dimension technologies. There are a number of variables in the mask and wafer costs. The first is the technology used. The smaller the dimension, the more expensive the masks. A second variable is the mask type. Using MLM (Multi-Layer Masks) results in putting 3 or 4 different mask layers on a single mask. This can result in up to a 75% savings in mask costs, but it also doubles the wafer costs. As a rough rule of thumb, MLM masks are cost effective when the total production volume will require less than 50 wafers.

Tekmos uses gate arrays in many of our designs. If there is a pre-existing gate array that we can re-use for a new ASIC, then we only have to make 6 to 8 masks, instead of the 16 to 27 layers required for a new mask set. And if we can use MLM masks, we can make a gate array mask set using only 2 physical masks.

IP

Many designs contain external IP that have to be licensed and purchased. While some IP is available for free, most have a cost ranging from $5K to $200K. The IP can range from oscillators to internal memory to external memory and bus interfaces. Also, most fabs charge extra for both the flash IP and the extra masks necessary to implement the flash.

Speaking of flash, and depending on the production volume, it may be more economical to include flash die in the package using stacked die assembly techniques than to license the flash IP. We use this approach on our legacy processors for program storage which replaces the old and unavailable EPROM technology.

Test Hardware

ASICs have to be tested, and we need test hardware to do so. For many digital parts, this can be as simple as soldering jumpers on a device personalization card. Some packages also require the design and implementation of a socketed load board. And analog parts may require the design of specialized measurement circuitry on a custom load board.

Some circuits may also require the construction of a probe card. Probing is required when we are selling die, when the cost of the package is high (as in ceramic), or when the design requires testing of pins that are not included in the final package (such as fuse based trimming for analog designs).

Engineering Time

The last factor of the NRE is the amount of engineering time that Tekmos has to provide. Some designs are ready to go, and only require a minimum of checks on our part. Other designs are in register transfer level (RTL), and must be synthesized and re-simulated. And other designs are “black box” (such as a 27 MHz radio receiver), which require us to do all of the design work. Another engineering task is if we have to write simulations for the design. We come up with an estimate of the engineering time involved, and that becomes part of the NRE.

Special Screening

Some parts, such as military parts, may require special screening. A major component of those costs is the design and fabrication of burn-in boards for use in burn-in and life testing. Tekmos uses outside services for the non-electrical screens, and each screen has its own lot charge. All of these are added to the NRE.

The Final NRE Amount

Based on the chip, Tekmos determines what is included in the NRE, and includes them to become part of the final, fixed price quote. And that is how we develop the NRE. Call us to get a NRE quote on your next ASIC project.