Two Approaches to ASIC Prototyping

There is always a risk that the first pass of an ASIC may not work as intended. This can be a result of a design error, a system integration error, or a marketing error in product definition. With ASIC tooling costs being high, most foundries offer a shuttle service. A shuttle works by putting multiple designs on a mask set. In this way, the mask charges are spread over all of the designs. A mask is typically divided up into 16 5x5mm squares. Each customer also gets 1 wafer, which will contain from 50 to 100 die, depending on if the wafer is 200mm or 300mm in size. Since a wafer lot has 25 wafers in it, customers can buy a limited number of additional wafers if more prototypes are needed. Eventually, the customer must purchase a full mask set for production.

Tekmos New SIP Business Card

Shuttle runs have another disadvantage in scheduling. They typically run every 4 to 12 weeks, depending on the process and foundry. Then, if the prototypes are good, the availability of production parts can take another 12 weeks of manufacturing. Most design cycles are behind schedule, and this additional delay can be painful.

Tekmos uses a gate array architecture on most of its designs, and that allows another alternative to risk management. In a gate array, the circuit size is generally known at the start. And gate arrays have a utilization factor, so a gate array is typically set at 30% larger than needed for a given design. This allows us to start the wafers prior to the design being complete. That alone can cut 3-4 weeks off of the prototype cycle. When the design is complete, we complete the programming layers for the gate array, and complete the prototype process.

In the event that the design doesn't work, we have to change the programming layers. Depending on the part, the design will have 3 to 4 programming layers, which is 6 to 8 masks. Since the chip contains from 25 to 27 masking layers, a revision increases the mask costs by 24% to 30%. This compares to a 6% increase in mask costs for using a shuttle run.

While at first, the advantage belongs to the shuttle runs, the reality is not so clear. Most digital parts do not need a revision. If fewer than 25% of the parts need a revision, the economics change to favor the gate array approach. And the schedule improvements are more dramatic. If no revision is required, then 3 to 4 months is removed from the production schedule. And time is frequently much more valuable than mask costs.

Our gate arrays are frequently designed to meet the requirements of a specific customer. In addition to raw gates, the layout may include embedded RAM, Flash, and mixed signal circuitry. Still, we are frequently able to re-use a given base array for a second customer. In that case, the economics strongly shift over to a gate array approach over a shuttle run. Every case has different economic considerations, and there are many cases where shuttle runs hold a clear advantage. Here at Tekmos, we consider all of these choice to make the most cost effective offering for our customers.