In this article, I would like to cover the choices behind making a masked ROM, and the design of the ROM array.
The first question that should be asked is why would anyone ever design a masked ROM when you have flash? It is a good question, and we have two answers. The first is that this ROM is being designed for high temperature applications, and flash memories lose their data at high temperature. Flash memories use stored charge, which will leak away over time. The leakage rate is a function of temperature, and roughly doubles with every 10C rise in temperature. A 10-year life at 125C reduces to a matter of hours at 275C. And that is if the flash is built on a fully depleted SOI CMOS process, which most are not. This reduction in flash lifetime can be partially addressed by frequent refresh operations.
A second reason for considering a masked ROM is that many processes do not support the flash technology, whereas all processes can be used to make a masked ROM.
Once the decision has been made to make a masked ROM, the next choice is the architecture of the ROM array. There are two options: NAND and NOR. NAND has better density, but is slower, and uses more power. NOR has worst density, but is faster and uses less power. In the past, all our ROMs have used the NAND architecture. This time, we opted to use the NOR architecture. At high temperature, everything runs slower. In computer systems, the memory speed is usually the bottleneck, and so it makes sense to design the ROM for maximum speed. Our initial design goal is to have a sub 100 ns access time at 300C.
The design of the ROM array is about as simple as possible. Each ROM bit consists of a single N-channel transistor. The source is tied to ground, the gate is connected to the word line, and the drain is connected to the bit lines through the programmable contact. If there is a contact, the bit line goes to zero. If there is no contact, the bit line stays as a one.
The poly word line resembles a transmission line, and it can take the signal a long time to go from one end to the other. We are using a special high temperature process that does not support salicide. Thus, the poly is quite resistive. We address that by running a metal line over the poly, and connect it to the poly every 8 bits. This greatly improves the ROM speed for those bits located the furthest away from the word line drivers.
The next thing that we should worry about is the impedance of the ground lines. This is aggravated by the use of Tungsten as an interconnect metal. We have to use tungsten because aluminum has metal migration problems at elevated temperatures. To lower the ground impedance, we run perpendicular ground lines every 64-bit lines that convert the ground line from a single stripe into a grid. This allows every ground line in the array to help lower the impedance.
We do have to add additional bits. The initial ROM was an array of 512 rows by 512 columns, for a total of 256K bits. We will group every 8 bit lines together to produce a single output bit. This produces a 64-bit word. To improve reliability, we are adding ECC to the ROM, which will require 7 more output bits, or 56 more bit lines. And we need to add one additional bit line which is always programmed to provide a reference for the self-timing. This will be discussed later.
At this point, I have an array with 512 rows and 569 columns. I will discuss the word lines and their decodes in a future article.