Sorry about the gap in the blog. It is a combination of new software, a surgery, and 4 solid days of customer visits and quality audits. When I left this, I had all but the bottom two address pins through LVS. I am putting that problem on hold, while I work on a bigger problem.
Within a few days after starting, I had a spice netlist that was a perfect match to the 68020. However, a spice netlist is almost useless for simulations. Just guessing, but a spice netlist of this size will take hours to simulate one clock cycle, and I need to simulate for millions of clocks. A simulation that takes 100 years to complete is not going to be useful.
I can model a transistor in Verilog, and the simulations will run a lot faster. Except for efficient Verilog I need to know which transistor terminal is the output, and which is the input. And that information is not available in the raw spice netlist. That is why I have been going through the spice netlist, and consolidating groups of transistors down into logical primitives that can be modeled easily in Verilog.
So I need a Spice to Verilog translator. A web search shows a number of tools, ranging in cost from free to expensive. I didn't see one that really inspired me, and so I decided to spend 4 hours to write my own. The links to Verilog are extremely important and I think that by having control of the translator I gain flexibility in dealing with unknown future problems.
I am old, older than C, and older than perl. So old that my preferred tool for netlist conversions is Basic, which has morphed into Microsoft Visual Basic Express edition. And that is so old it is free.
The conversion from Spice to Verilog is really pretty easy. It is a lot easier that going from Verilog into Spice. There are two issues that have to be dealt with. Spice allows node names to start with a number, and that is illegal in Verilog, unless you use an escape name. I am not a big fan of escape names since I do a lot of layout work with Spice, and the backslash character is not a legal Spice note name. I spend a lot of time modifying escape names, and so I don't like creating new ones.
The second issue is that Spice does not have the pin names for primitives embedded in the netlist. I can address this by either making the translator read the libraries, or providing a reference table with the appropriate pin names. Because this is not a commercial product, I choose the easier lookup table approach.
This design is likely to have a hundred different spice files when I am done. I have the choice of making my program read a list of files, and processing them sequentially. Or I can put together a batch file that will append them into a single file. The latter approach is easier, and so I choose that one.
Knowing what to do is the hard part. The coding is simple, and now I have my Spice to Verilog translator. My next step is to develop the Verilog library that accurately models my dynamic logic primitives. And that will be the topic for my next blog.