Low Cost Methods For Including Flash in Designs

Including flash on an ASIC die involves tradeoffs. While flash is available in most processes, you need to be using a process of 90nm to 65 nm to start obtaining reasonable flash densities. But these processes have a substantially higher NRE, which is only justifiable with higher volumes. This is a particularly painful tradeoff when all of the other requirements can be met with a 130nm, 180nm, or even a 350nm technology.

Another complication with flash is that each die requires a data retention test, which consists of writing a pattern into the flash, and then baking the wafer for a day at around 250C, followed by a second probe test that verifies that the pattern is still present in the flash. The cost of test is a significant factor in the final product cost, and adding two additional tests is a serious increase in product costs. Flash manufacturers mitigate this cost using special probe cards that can probe an entire wafer at the same time, but this is generally not feasible for an ASIC.

Our preferred approach is to purchase flash KGD (Known Good Die), and assemble the part on top of our ASIC in the same package. The flash and the ASIC can be background so that they will both fit in the 0.8mm thickness of a QFN package. The assembly cost does rise by an amount related to the number of additional internal bond wires, but this can be reduced if it is possible to use a serial flash in the application. And either way, the increase in assembly cost is much less that the increase of test costs for embedded flash.

There are design challenges with interfacing an external flash with the ASIC requirements. Writing to, or erasing the flash can make it unavailable for code execution. The bus width of the flash may not align up with the chip requirements. And the flash access time can act as an upper limit on an embedded processor’s speed.

There are design techniques that can be used to address these challenges. A small ROM can be included that will contain the processor code for flash write and erase operations, though care must be taken to deal with interrupts that might occur during flash operations. The bus width and speed requirements can be met by transferring the Flash contents to RAM for execution. And the use of cache can allow the execution of code out of a large amount of flash.

Tekmos has used this technique to add flash to our designs for 18 years. It is used in all of our microprocessors, and in our flash memory offerings. Contact us to find out how we can add flash to your SOC application.  Contact Tekmos Sales

Date

2019-06-04