Word Line Drivers

In my last article, I discussed the design of the ROM bits. This article will cover the word line drivers.

Our ROM has 512 word lines. A brute force approach would use a 10-input AND gate to decode each word line, nine inputs for the address lines, and the tenth input to disable all word lines during precharge. But 10-input AND gates are both large and slow, so a better way must be used.

We use a 2-to-4 demuxer for eight of the address lines. The ninth address line is gated with the precharge. This allows a 5-input AND gate to be used instead of the 10-input gate. But this solution also has problems. In a NOR ROM, the word line drivers must be the same height as the ROM bit. And that is not enough room to put in a AND gate.

The next solution is to create a double height word driver that can decode both words. The schematic changes to a 4 input NOR gate that drives a pair of 2-input NAND gates, each driving a word line through inverters. This is a tight fit, but can be made to work by mirroring each dual word line driver so that they can share common supplies. Three of the four inputs of the NOR gate are common between the two mirrored drivers, and that saves more room.

The NOR and NAND gates are minimum sized devices, while the word line has 569 loads. In order to drive large loads, it is necessary to use a chain of inverters, each one being stronger than the preceding one. The optimum ratio between inverters is "e". But using "e" as the ratio results in a very large inverter driving the word line. And that means 512 large inverters for all the word lines.

We resolve this by letting the final ratio be a larger number. There is a tradeoff between reducing the inverter size, which increases the ROM access time, but reduces the area and reduces the peak current draws. After multiple spice runs, we set the output inverter ratio to be about 95:1. This also allows the inverter chain to be three inverters long. One thing that worked in our favor is that the bit cells start to conduct as soon as the word lines exceed the N-channel threshold, which is close to the starting voltage.

The address lines A6:A14 control the word decode. We have the option of latching them during the ROM read cycle, or not. If we choose to latch them, then we can either include the latches in the ROM core, or latch them externally. It is not required to latch the addresses, but it is safer to do so. Our final decision will be determined by the physical layout. If there is room for the latches, then we will add them. If not, we will leave that as an option for the chip level designer that uses this ROM core.

In the next column, I will cover the bit line muxes, the sense amps, and the ECC logic.

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Date

2017-10-18