RISC

Tekmos serves several high reliability markets, such as aerospace, military, and oil. It is therefore only natural that much of our internal R&D efforts are directed toward increasing the reliability of our products. One of these efforts is aimed at improving the reliability of processors. One way to do so is using a triple redundancy for all flops in the processor, a technique called RHBD (Rad-Hard By Design). This works, but is a brute force approach that at a minimum, triples the circuit size. We have another approach that may only add a 30% overhead.

To verify this approach, we need a processor to try it out on. There are many processors out in the market, but they come with licensing fees and restrictions on changes to the internal architecture. And we need to modify the internal architectures.

So, we chose the RISC V processor, which is an open source processor from Berkley. An interesting aspect of this processor is that it is defined by the instruction set, rather than the hardware. The RISC V processor is finding increasing acceptance, and is supported by several development tools.

Our first step was to get the basic design up and running in our simulator. Then came the more difficult task to fully understand the design. This is where we are now. Next, we use the RISC V as a test bed to prove out our reliability concepts. What is next beyond that is a little uncertain, and is more of a marketing decision. Check back with us in a year and see how it turns out.

Date

2017-07-10