Part V Design of Dual Port RAM

In this final article about RAM design, I am going to discuss the timing necessary to make the RAM work.

Between memory cycles, the RAM is in a precharge mode. All bit lines are being held at Vdd. All word lines are off. And the data latches are holding the last value that was read or written.

The cycle begins when a chip enable signal is clocked into a flop. In a synchronous RAM, the clock is the RAM clock. In an asynchronous RAM, the clock is derived from a change in address lines. The rest of the RAM timing is asynchronously derived from the output of this flop. This means that the end of one step triggers the next step. Here is the sequence of RAM timing:

1. Turn off the precharge circuits and put the data out latches into a read mode.
2. Turn on the word lines.
3. Delay for enough time for the read data to be present on the bit lines.
4. Enable the sense amps
5. Latch the data into the output latches.
6. Turn off the sense amps.
7. Turn off the word lines.
8. Enable the precharge circuits.

Item 3, the read delay, is the difficult step. The time necessary for the bit cells to charge the bit lines is the major component of the memory access time. It needs to be just long enough for the bit lines to have enough differential voltage so that it can be detected by the sense amps. If it is too long, then the memory access time has been unnecessarily increased. But if it is too short, then the data cannot be reliably read, and the memory will fail. The trick is to create a delay of just the right length, plus a small bit of margin.

One way to do this is to add one additional bit line to the array, with the data in the bit cells connected to this line hard wired to zero. Since the extra bit line is part of the array, its timing will exactly duplicate the timing of the other bit lines. This bit line is fed into a ratioed inverter whose threshold is set just beyond the sensitivity of the sense amp. The buffers on the output of the inverter provide additional margin.

Setting the inverter threshold is a classic engineering tradeoff between speed and margin. While pure RAM designers go for speed, there are other considerations for ASIC RAM designers. This RAM is going in an embedded array that will be re-used in different applications. As a result, I must assume a wider temperature range. Instead of the commercial -40C to +85C, or the military -55C to +125C, I need to have it work -65C to +150C. Analog is always the weak link in a design, and I can't have the RAM be the first thing to fail. The design must also work over a wider supply range. The ASIC may be powered off a battery, which can require the minimum voltage to be on the order of a volt. And the easiest way to achieve these goals is to adjust the inverter threshold to give more margin at the expense of speed.

I can also build multiple inverters, and allow the metal programing options to select the inverter ratio. This lets me vary the speed versus margin on a customer by customer basis.

And that is how you build a dual-port block RAM.

Date

2017-03-20