Part IV Design of Dual Port RAM

The Sense Amps Part IV

This is the fourth in a series of articles on the design of a dual port RAM.

When a memory is read, the word line enables a row of bits. Each bit is connected to two bit lines, and depending on the state of the bit, will pull one or the other to ground. The bits are weak, and there is a lot of capacitance on the bit lines, so it will take a long time to drive a given bit line to zero.

A sense amp is an analog circuit that is designed to sense very small differences in the two-bit lines, determine which line is going to ground, and which is remaining at the supply. The sensitivity of the bit lines is key to setting the memory access time, since the faster the difference can be detected, then the faster the data is available.

The sense amps' circuitry also provides a bit line precharge, bit line multiplexers, output multiplexers, and the write circuitry.

The Precharge

Before the memory can be read, the bit lines must be precharged to Vdd. This is accomplished by relatively large transistors that short the lines to Vdd. In addition to the two-bit line transistors, there is a third transistor that shorts the bit lines together. This insures that the bit lines start out with the same values prior to the beginning of the read cycle.

Instead of having a precharge cycle at the beginning of the read cycle, precharge is designed to occur in the resting state, which the processor enters at the end of a read cycle. Using large transistors means that the circuit is quickly precharged, and is ready for the next read cycle.

Bit Line Multiplexers

While every bit line needs a precharge circuit, every line doesn't need a sense amp. Doing so would be a wasteful use of power, and besides that, there is not a lot of room for that many sense amps.

Memories are organized in roughly square arrays. Our design is organized as 256 rows by 72 bits. We use a two to 1 multiplexer to connect 4 bit lines to a single sense amp. This memory is unusual in that we have word widths ranging from 1 to 36 bits. Had this been a x9 memory, we would have used an 8 to 1 multiplexer. To prevent errors in the read data, a precharge circuit is added to every internal node in the multiplexer.

The Sense Amp

The sense amp itself is just a cross coupled inverter pair that is powered through a sample clock. Transmission gates connect the inverter to the output of the bit line multiplexers. The presence of a small difference in bit line voltage levels is enough to cause the sense amp to settle in as high or low when the sample clock occurs.

My favorite analogy for a sense amp is to consider a ball that is perfectly balanced on a hump. Just the slightest difference in the bit line voltages is enough to cause the ball to fall on one side or the other.

To make the sense amp work perfectly, it is very important to make sure that the layout is perfectly symmetrical between the two-bit line sides. Any difference will tend to influence which way the sense amp switches. This can be compensated for by delaying the sample clock to allow more margin (i.e. more voltage difference) on the bit lines. Of course, this comes at the cost of increasing the RAM access time.

Output Multiplexers and Drivers

Once the sense amps have determined the data, it is stored in output latches. We will store 36 bits every read cycle. Then we will use another set of muxes to step the data down to the programmed data width.

Writing Data into the Bits

In comparison to reading, the write cycles are trivial. All that is required is to force a zero on one of the bit lines. When the word line is selected, data is written into the bits. Because the width of the memory is programmable, we might have to write to a single bit. We accomplish this by just not writing to the other bit lines. Keeping both bit lines high is just a read cycle as far as those bits are concerned and does not disturb the data.

Next Time - Self Timing

For the RAM to work correctly, the sample clock must be positioned at the exact correct point to optimize trade offs between signal size and RAM access time. I will explain self-timed RAMs next month.

Date

2017-02-20