High Temperature ROM Design

In the previous two articles, we discussed ROM bits and word drivers. In this article, we will discuss the sense amps. Or more accurately, we will discuss the bit line precharge, the multiplexor, the sense amps, and the output latch.

In the ROM, the bits can only pull to zero. To ever get to a logic one, we use a precharge circuit. That is a fancy name for a P-channel transistor. In between read cycles, the bit lines are kept precharged. When a read occurs, the precharge lines are turned off, and then a single word line is turned on. Depending on whether that bit has been programmed, the bit line will either remain at a one, or be pulled down to a zero. After the end of the cycle, the bit lines are precharged back to the one level. The size of the precharge transistor is not that critical. It must be large enough to precharge the bit line before the next cycle occurs. Generally, this can be accomplished in 3 or 4 nanoseconds.

The most difficult thing about the precharge is the layout. Since there is one for every bit line it must fit within the width of a bit. In our case, the bit was so narrow that we could not make the precharge fit. As a result, we staggered the precharge transistors, taking up twice the height so that we could maintain the required width.

After the precharge is an 8:1 mux. This consolidates 8 bit lines down to a single signal that will feed the sense amp. The mux is built out of N-channel transistors. They are arranged as 2:1 muxes in 3 stages, going from 8 to 4 to 2 to 1 signal. There is a slight complication in that each individual mux stage also requires a precharge. So, in addition to the 8-bit line precharges, we have to add 7 mux precharges. The mux is controlled by address lines A3, A4, and A5.

The sense amp is quite different in a ROM than in a RAM. In a RAM, there are complimentary bit lines available, and the sense amp makes a differential measurement. Differential measurements are quite easy to make in MOS technologies. However, in the ROM, there is only a single bit line available. One might create a voltage reference, but there are difficulties in making a valid reference, and the margin available is only half that of a true differential signal. Instead of a voltage reference, we use time as a reference. We add one additional bit line to the ROM that is always programmed as a zero. This extra bit line closely tracks the performance of the rest of the ROM. So, when it reaches a zero level, we know that sufficient time has passed for any other bit line that is switching to a zero to reach a zero level. This turns the sense amp into a simple inverter. This inverter then feeds a latch. We make the latch transparent at the beginning of the cycle, and close it when the reference bit line reaches a zero.

Starting from 568 bit lines, the muxes narrow it down to 71 bits, and those are stored in latches. The number 71 comes from 64 data bits and 7 error correcting bits. In our next article, we will cover how the ECC circuitry works, and how we wind up with a final data bus of 8, 16, or 32 bits in size.

Date

2017-02-19