TK68HC811E2

We are changing the format of the newsletter slightly, and will cover one of our parts each month.  This month, I will talk about the TK68HC811E2.

The TK68HC811E2 is one of our older processors, and dates from the late 70s.  It uses the HC11 core, and is noteworthy in that it has 2K bytes of EEPROM.  In an era when all other micros were One-Time-Programmable (OTP), it was one of the first re-programmable processors.  As such, it found its way into many industrial systems and is still in use today.

This was an evolutionary dead end for Motorola.  The EEPROM could not keep up with the densities being achieved with EPROM, and so Motorola did not use the EEPROM approach with other members of the HC11 family.  Nonetheless, the part has survived to the present time.

When Tekmos started to reverse engineer the HC11 family, we created a common gate array to implement the different family members on.  We chose to include 768 bytes of EEPROM on this array, along with 768 bytes of RAM, and 24K of ROM.  We did so knowing that this prevented us from making the 68HC811E2, as well as the 68HC11F1, which had 1K of RAM.

Then we came across an opportunity for the 68HC811E2.  The opportunity was large enough for us to create a new gate array for the chip.  Our basic EEPROM memory is a 256 x 8 cell.  We have a layout that includes 3 of these cells, along with a charge pump and a band gap voltage reference.  The layout was made to support up to 4 EEPROM cells, giving a total of 1024 bytes.  

The original gate array had a stack of EEPROM and RAM on the right side, and a stack of ROM on the left hand side.  Starting from this gate array, we modified the right stack, removed 256 bytes of RAM, and added256 bytes of EEPROM.  Then we removed the 24K of ROM, and copied the memory stack from the right side to the left side.   This gave us the array that we needed for this product.

The rest of the design came from our 68HC11E1 design, with appropriate modifications.  As is or policy, we put the design into a FPGA based emulator and verified is in the customer system prior to making silicon.  We did have a few issues with the design and have revised it to better match the original chip performance.  

Testing is proved to be another challenging area.  An EEPROM byte takes 10 ms to write and 10 ms to erase.  That works out to 40 seconds per pass.  With a few passes, the test becomes really long.

Another interesting aspect of the TK68HC811E2 is that we are selling this part as a 175C part, and that has its own set of challenges.  We use a special high temperature bake to guarantee longer data retentions. We use aluminum bonding to increase the reliability of the package.  And we test at high temperature, which is difficult and time consuming.  It takes about 1 minute for the part to reach temperature, and another minute for it to cool off enough to be removed from the test fixture.  This limits our capacity to about 15 units per hour.  We have plans to address that, but I will wait to another letter to elaborate.

We are exhibiting this month at the HiTec conference in Albuquerque, and will be featuring this part there.

Date

2014-05-05