FPGA Conversions

An FPGA conversion consists of creating an ASIC from the same design files that were used to make an FPGA.  Customers do this to either replace an FPGA that has been discontinued, or as a cost reduction for a product that has increased in volume.  The main tradeoff in an FPGA conversion is the expense of the NRE against a lower unit cost.  This number breaks even with a volume of about 1000 units.  For obsolete FPGAs, the cost of the NRE has to be contrasted against the other options of a system redesign or the availability of parts on the gray market.

Tekmos asks several questions before doing an FPGA conversion.  How big is the design?  How fast is it?  How much RAM does it contain?  How many pins does the design use? What type of package is required?  Does it contain someone else's IP?  Are there simulations? There are reasons behind these questions.

How big is the design?

This question may also be phrased as "What is the utilization?"  Both questions yield the design size.  The design size determines the size of the ASIC necessary to implement it, and that determines the cost.  The size also roughly corresponds with the amount of engineering work that we will have to do during the conversion.  And that has an impact on the NRE charges.

How fast is it?

This is our way of determining the process technology that I will need to implement the ASIC in.  FPGAs have been technology drivers, and are always pushing the wafer fabrication limits.  Fortunately, an ASIC can be 2 to 3 generations behind an FPGA, and still provide the same performance.  This is because a gate is inherently faster than the CLBs used inside of the FPGA for logic functions.  Also, many customers do not use the FPGA anywhere near its speed capability.  If we can use an older technology, we may substantially reduce both the NRE and unit price.

How much RAM does it contain?

Starting in the 1990s, the FPGA manufacturers began including large amounts of RAM in their designs.  This makes it difficult to replace an FPGA with an older technology ASIC.  And using the same technology increases the NRE costs, which in turn increases the minimum break-even volume.  Of course, even if an FPGA contains 8 MB of RAM doesn’t mean that the design is using it.  By knowing the RAM size, we can determine that a less expensive technology can be used.

How many pins does the design use?

Many FPGAs come in a high pinout package.  Frequently, ASICs are pad-limited.  This means that the area of the ASIC is determined by the pitch of the bonding pads along the side; in this case, the cost is proportional to the square of the number of pads.  If the customer is using fewer pads, we can use a smaller ASIC.

The test cost may be affected by the pin count.  Inexpensive testers are generally limited to about 256 pins.  The test costs increase for the 256 to 512 pin range, and they become very expensive above 512 pins.

Using fewer pins can also allow for the use of less expensive packages.

What type of package is required?     

Many FPGAs come in a BGA package.  These packages are usually not open-tooled, and thus require an additional NRE to create the substrate.  This affects the NRE.

Does the design contain someone else's IP? 

There are cases where the customer does not own their own design.  For example, if your design uses an FPGA with a built-in PowerPC processor, then we can’t make the ASIC until a license for the PowerPC is acquired.  Even if the license is available, the expense of the license may make the project uneconomical.

Are there simulations?

We need logic simulations to do a successful FPGA conversion.  We cannot use SCAN, because while SCAN will verify that every gate is functional, it will not help to determine if the design will still work in the ASIC technology.  FPGAs use CLBs, and ASICs use gates.  So while an inverter and a NOR gate have the same CLB speed in an FPGA, their speeds are quite different in an ASIC.  We need the simulations to exercise the design, and prove that the FPGA design still works as an ASIC. 

We will frequently use our simulations to verify on our tester that the FPGA design matches the proposed ASIC.  This is a good way to catch the occasional case where the design files don’t match the production version of the code used to program the FPGA.

Implementation

For most FPGAs, it takes about 4 weeks to convert the design, and another 8 weeks to manufacture prototypes.  Production can begin about 2 weeks after prototype acceptance.

Date

2013-04-28