A Stopped Clock is Always Right Twice a Day

I haven't written much lately about our 68020 reverse engineering, because I haven't made a lot of progress.  We had created a Verilog netlist, but the chip wasn't getting out of reset.  And with no reference, I spend months chasing dead ends.

Eventually, we came up with the idea of running spice on the raw netlist, and using those results to check the Verilog.  We quickly identified a problem with the clocks.

A design issue in any processor that interfaces with a slower bus is what does the processor do when it is waiting for the current bus cycle to complete.  There are generally two options.  The first is to have some sort of pause command that freezes the processor.  The second is to stop the clocks and wait.  In general, you cannot stop the clocks in a circuit with dynamic logic, and so I was convinced that there has to be some sort of freeze command.

Spice said that I was wrong.  In the 68020, if the processor needs to wait, then 3 of the 4 internal T clocks are stopped, and only T4 keeps running. This stops the microcode ROMs, and prevents the processor from advancing to the next state.

There is a lot of analog circuitry around the clocks, and some of it was designed to stop the clocks.  When I had replaced the clock generator with digital Verilog code, I had missed this.  And the price for missing it was 6 months lost.  Ouch.

Once we fixed this problem, we started to make a good deal of progress.  We now have 31 of the 49 simulations passing, and the end of this project is in sight.

Date

2013-05-04