Does anyone really know what time it is

Clocks. The 68020 contains at least 6 of them, generated from a single input clock. But it is not clear what the timing relationship between them is. And this matters because a number of the strobes are used in the ROMs to control timing.

So, what exactly is PH1, PH2, T1, T2, T3 and T4? And how do I find out?

The simple answer is to extract the netlist from the clock generator, and run spice on it. With only one input, it should be easy to see what comes out.

Hah.

Nothing is ever easy in spice and in analog. This is why analog designers make the big bucks.

Extracting the netlist was easy, and in only took a few iterations to fix the broken nodes that invariably result from my netlist extraction. In the 68020, the original layout people ran nodes through adjacent cells. So when I take the clock generator cell, I find several key nodes are now cut into separate pieces. It is not hard to refer back to the whole layout to determine who is hooked to whom, but it is somewhat tedious.

I don't have any information about the original 68020 process. So I decided to use the models from one of my current processes. And that lead to problem number 1. My current processes do not support depletion devices, and they are all over the clock generator. At first, I thought that I could just adjust the threshold of a NMOS model to a negative number. Well, I can, but that doesn't work. There is a lot more than threshold that determines depletion characteristics. When all else fails, turn to Google, and I found my model out on the web.

And now I was faced with problem #2. Nothing worked. Period. Clock in = DC outputs.

Back in the old days, it was difficult to make a TTL compatible input, particularly for a critical signal such as clock. The input stage has the clock capacitively coupled into another node that provided the drive for the input stage. This node was very sensitive to both the value of the capacitor and the strength of a depletion device that provided a DC bias. I spent some time fiddling and estimating, and was finally able to get it to work.

This made PH1 and PH2 work, but the T1 – T4 strobes remained a mystery.  Here is a pretty picture of the two phasesand the input clock.  The difference in pulse widths is a function of the values I chose for the depetion strength.

I continued to work, making incremental progress. I found little things, like a transistor whose source needed to be connected to Vdd (another cell extraction error). But all I saw was weird levels. Here is one of them, and it sure doesn't look like a clock.

And then I noticed that it was not as weird at 200ns as it was at 0 ns. So I ran a much longer simulation, and the design started working. There were a lot of floating nodes that needed a few clocks to arrive at the correct voltages. Sort of like an old car engine that you have to crank for a while before it starts running. Now I know that T1 – T4 are in consecutive order, they run at half the frequency of the main clock, and that T1 (and T3) are aligned with PH1.

One interesting thing was the design of the drivers for. They have an n-channel device as a pullup, and they are using a bootstrap circuit to generate 8 to 10 volts on the gate so that it can achieve a good one level. This is shown in the picture below. Since this is a CMOS process, I have to wonder why they just didn't use a CMOS driver. Were P-channel devices too slow back then? Were they worried about area?

This plot shows the bootstrap node in red, approaching 10 volts in magnitude.  In modern processes, this would casue the gate to rupture.

Enough of worrying about the past. I need to push on.

Date

2012-01-10