Wrapping up the MICROROM

I continued my work on the MICROROM.

There were two different types of sense amps. Inverting and non-inverting. It took me a moment to realize why. One of the things that limit speed is the rise time of the bit lines. And the rise time is related to the number of programmed bits on each line. In a worst case situation, you have all but one bits programmed. However, if you allow the sense amp to be optionally inverting, then you can select those cases where more than half of the bits are programmed, and invert both the programming and the sense amp. Presto. You have no bit line with more than half of the bits programmed, and the worst case delay is cut in half.

Except that in this case, you have 8 separate bit lines combined into a single bit line. And since the timing is set by the worst case on an individual bit line, you can still do this trick and not gain anything. One could try a more complicated sense amp with the decision to invert or not invert tied to a mini-ROM depending on the individual bit line. But that was not done here. It does make it a little tougher to decode.

Another confusing thing is that the word lines are not in consecutive order. They don't have to be, but I have never seen them not in order before. Perhaps that is a feature of microcode that I never learned to appreciate.

99% of the ROM was word lines, bit, and sense amps, and that went easily. The balance was the timing generators. There were only about 20 gates, so I copied them down, one at a time, and checked my work by running LVS. Twenty five iterations later, and I have a SPICE netlist that exactly matched the ROM.

Normally, I would then run some Verilog simulations to see if it worked. But this ROM uses timing strobes called T2, T3, and T4. And I don't know what they look like. There is a clock generator block where they come from, along with Phase 1 and Phase 2. This block has one input and six outputs, so I will just SPICE the resulting netlist and see what the waveforms really are. I don't think I will be using all of the phases in the final netlist, since I will use static logic everywhere. But I do need to know what they are now.

Date

2011-12-05