LVS Text Layer

The layout has about 20K texted nodes, and about 8K are unique.  I made the decision to use these named nodes as LVS text in our design flow.
So I selected the text, and mapped it to LVS text layers.  Then I ran a LVS, and looked at the error report.  There were around 100 text errors.  Some text was misplaced.  Since the original text had been a comment, it was not necessary to attach it to a given polygon.  So some of it was out in the field.  Occasionally, it looked like someone had moved a group of metal lines, and had not selected the text.

In other cases, the same text was on two different nodes.    Some of these were don't cares, and others were confusing.  In the latter case, I just deleted the text.  After all, it is supposed to help, not hurt.

There were a few cases in PLAs (Programmable Logic Arrays) where nodes had been labeled 0 to 7 on one side, and 7 to 0 on the other side.  I looked at other arrays, and picked the most common approach as standard, and adjusted the text accordingly.

And finally, the chip had multiple VSS and VDD connections.  The VSS connections were all common through the substrate, but the VDD connections were definitely separate.  This mainly involved a few IO buffers that had independent supplies.  I thought about this and decided that I would connect all of the VDD supplies together for my analysis work.  They can be separated later if necessary.

I was a little concerned that I might accidently modify the original layout, and thereby introduce errors into my later work.  So I put the original files into a reference library, and created a working directory for my work.  This allows me to add text and cad layers without affecting the original.  

The original design contains test transistors and alignment marks.  I created duplicate cells for those devices in my working directory so that they would replace the originals.  These duplicates don't contain anything but text, and so I don't wind up adding test transistors to my ultimate netlist.

Date

2011-08-02