Its Alive

It has been a while since my last post.  This project still hasn't been funded, and so I can only work on it in my spare time.  And lately I have been working on a similar PowerPC project.  But today was different.  We lost our phones and internet connection at work, and suddenly I had spare time on my hands.  So I tackled the 68020 with a vengeance.

I took my Spice netlist of the 32 address pins, consisting of logic primitives, and ran a program that I wrote that converts Spice into Verilog.  I wrote a library describing the logical behavior of my Spice primitives.  I put all of this together into a Verilog simulation and ran it.  It didn't work.

I traced it down to a dynamic precharge on a circuit that accelerates the carry for the 32 bit counter.  After studying it for a while, I am convinced that while this circuit will work most of the time, it may not always work.  This is the sort of thing that can make a circuit fail once every month.

I put a Verilog pullup resistor on the node which prevents the illegal state.  Then I re-ran my simulations, and it worked.

I now have a 32 bit counter that can be loaded, saved, and incremented.  And I can now put it next to a full RTL implementation and use it to verify the RTL.

This is now a complete verification path for the digital logic from layout to Verilog.  Next I will do a ROM.  The ROMs will be reverse engineered with a different approach.  I would like to  figure out a way to read the programming data directly, and then stick that back into a separate ROM.

To be continued.

Date

2011-11-17