Data Bus Pin

I chose a data bus pin as my next cell. At least I know what it is supposed to do. Each pin consists of output transistors, and the drivers for those transistors. The output buffers use N-channel pullups instead of p-channel pullups. I find that unusual, as it is hard to get a good one level with that approach. There have been reports of level issues with this chip, and that may be why. I am strongly inclined to use CMOS outputs, but that is something that will be decided later. I isolated a cell and extracted the netlist. I am always interested in seeing how people create the tristate output drivers. In this case, there appears to be a latch on each output transistor, with the tristate signal clearing both latches. There is a third latch that drives the two output latches. Since 2 latches = 1 flop, I wonder if there is some sort of output flop here. The clocks don't seem right for a flop, but this could be a case of me not recognizing the logic. I also note that each bit can be written to and read from each byte on the internal data bus. The pin D0 can go to d0, d8, d16, and d24 on the internal data bus. The buffers also have a data precharge for their respective bit on the internal data bus. And there is a test mode that allows the data bus to directly drive something else. I think that is a rom address, but I haven't traced out the wires.

Date

2011-08-10