Clean LVS Run

Because this project is not yet funded, I can only work on it nights and weekends.  And since I had to stay around the house last weekend, it was a perfect time to work on it.  I do think that we will be funded, and I would like to make as much progress on understanding this chip as I can before that happens.

After deciphering the XOR gate, I was able to get a clean LVS run on a single address output buffer.  But are all output buffers identical?

I took the layout, and isolated the data bus pads.  This is easier said than done.  There are lots of embedded logic blocks that are in the pad portion of the layout, but are not part of the pads.  These have to be removed so that they do not obscure the results.

Another problem is that the layout cells are area-related rather than design-related.  Thus, if I remove a stray logic block, it is likely to remove a portion of the buffer control bus, leaving opens.  And these have to be fixed.

I discovered that the data bus pins 0-14 are different from 15-31, in that the higher data bus pins do not have the test input logic.  It was pretty easy to copy the original cell over and then remove the test no2 gate.

With the data bus clean, I turned to the address bus.  Again, I had to go through and isolate just the address pins.  Because of the carry being inverted on each stage, I made two address buffers; one with a positive carry and one with a negative carry.  I noted that the first bit, a2, did not have a carry input.  The gate was still there, but had been hardwired to ground.  That sort of worked, but I had a lot of errors on the higher address bits.  

On examination, I noticed that address lines 2-16 had a wired or output called csensea (carry sense address?).  When the lower bits were all 1, this signal went to a 1 and became the carry in for a17.  A17 to a31 did not have the csensea circuit.

The csensea line had a n-channel pullup that I thought was odd, since that does not produce good levels.  I would have expected a depletion device.  The signal then went through a level shifter before it was inverted again and became the carry input for a17.

I can see the need for it, since it doubles the speed of the address counter.  Still, the exact implementation seems a weak link.  I think we will use a logical solution in our version.

With these changes, everything passed except for a0 and a1.  These two bits are totally different, so I isolated them so that I could extract their netlist.  At this point, my weekend was over, and they will have to wait for my next stray moment.  

Once I finish the address pins, I think I will skip the remaining pads and start looking at the ROMs. The other signal pins seem to be heavily involved with their control logic, and I need to spend my time on different areas of the chip.

Date

2011-8-22