Address Pins

I started working on the address pins today.  I selected them all, and noticed that there were a lot of difference cells involved.  That is not a particularly good sign, since that could mean a lot more work.  So I adopted an optimistic attitude that they were likely just layout variations, and picked one for analysis.

The analysis consists of isolating the cell, and using LVS to extract the netlist.  Then I sort through it, identifying things that I understand, like inverters and latches.

This time, though, I came across a 4 transistor structure that was not connected to a supply, and that I could not recognize.  I spent all afternoon studying it.  And then it struck me.  An exclusive-or gate!

Many years ago, when I was a mere youth at Mostek, the designers came across a trick to make an exclusive-or gate out of 4 transistors.  Because of the novelty, the designers just had to use it, and it was designed into one of our dialer chips.  It worked, but not well at low voltages.  It actually was the first thing to stop working in our chip at low voltages, and we had to remove it in a subsequent design.  There were tense meetings as it was explained how a clever trick had killed a chip and delayed our schedules.  And now here it is again.

I am going to provide a spice model of the xor gate for those who have not seen one before.  Logically it is the same as any other exclusive or gate, except that the b input is complimentary.  Also note that there are no supply connections.  This makes for a great interview question, for those who enjoy destroying interviewees.

Spice, z=output, a = input, b and bn are complimentary inputs.
mp1  z  a  b  vdd   pmos
mp2  z  b  a  vdd   pmos
mn1  z  a  bn 0     nmos
mn2  z  bn a  0     nmos
 
With the XOR gate, it became obvious that the address buffers contain both the current value of the address and the ability to increment the address.  There is a section of the execute unit that is labeled PC, and I have interpreted that as the program counter.  But the address buffers may contain either the program counter, or a mirror image of it.  And the ability to increment the address buffer will improve the address access time, which is critical timing for the cycle.

Date

2011-08-15